Relaxed restriction for uppercase BLIF model names

chipsalliance / f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

https://f4pga-v2x.readthedocs.io/en/latest/

Apache License 2.0

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Relaxed restriction for uppercase BLIF model names #87

Closed rw1nkler closed 3 years ago

rw1nkler commented 3 years ago

This PR removes assertion for upper case BLIF model names.

mithro commented 3 years ago

Why do you want to remove this?

mkurc-ant commented 3 years ago

@mithro This feature has been requested by QuickLogic. They wanted to be able to directly support their flip-flop primitives in VPR in the same way as their proprietary tools do - without the need of Yosys techmap. The flip-flop cell is named ff (lower case).

If you find the change unfeasible we can stick with the techmap approach (map ff into FF).

mithro commented 3 years ago

@mkurc-ant - I think the techmapping approach is a better solution.