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chipsalliance / f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.
Apache License 2.0
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BUFHCE route-through handling #52

Closed mkurc-ant closed 3 years ago

mkurc-ant commented 3 years ago

This PR removes explicit BUFHCE insertion while they are configured as a route-through (ie. permanently enabled).

mkurc-ant commented 3 years ago

I've rebased the PR. The CI is failing due to golden references mismatch after the change. Once I test it against symbiflow and make sure that everything works ok I'll update the reference files.

mkurc-ant commented 3 years ago

There are consecutive failures on many xc7 designs from symbiflow, all on the same assertion:

Traceback (most recent call last):
  File "/home/build/mkurc/symbiflow-arch-defs/env/conda/envs/symbiflow_arch_def_base/lib/python3.7/runpy.py", line 193, in _run_module_as_main
    "__main__", mod_spec)
  File "/home/build/mkurc/symbiflow-arch-defs/env/conda/envs/symbiflow_arch_def_base/lib/python3.7/runpy.py", line 85, in _run_code
    exec(code, run_globals)
  File "/home/build/mkurc/symbiflow-arch-defs/third_party/symbiflow-xc-fasm2bels/fasm2bels/__main__.py", line 15, in <module>
    main()
  File "/home/build/mkurc/symbiflow-arch-defs/third_party/symbiflow-xc-fasm2bels/fasm2bels/fasm2bels.py", line 489, in main
    top.make_routes(allow_orphan_sinks=args.allow_orphan_sinks)
  File "/home/build/mkurc/symbiflow-arch-defs/third_party/symbiflow-xc-fasm2bels/fasm2bels/models/verilog_modeling.py", line 2174, in make_routes
    self.handle_post_route_cleanup()
  File "/home/build/mkurc/symbiflow-arch-defs/third_party/symbiflow-xc-fasm2bels/fasm2bels/models/verilog_modeling.py", line 2347, in handle_post_route_cleanup
    site.post_route_cleanup(self, site)
  File "/home/build/mkurc/symbiflow-arch-defs/third_party/symbiflow-xc-fasm2bels/fasm2bels/models/clk_models.py", line 191, in cleanup_hrow
    assert False, bufhce_i_wire_pkey
AssertionError: 1627284

From initial debugging I conclude that it happens when a single clock net drives multiple route-through BUFHCE. When one is removed input of the other one(s) is orphaned.

acomodi commented 3 years ago

@mkurc-ant To solve the license check issues, this solution can be used, at least temporarily.

mkurc-ant commented 3 years ago

@acomodi Thanks, I'll exclude golden verilog files as soon as I confirm that fasm2bels works correctly.

mkurc-ant commented 3 years ago

@acomodi Can you review again?

mkurc-ant commented 3 years ago

@acomodi Yes, I'have tested this change against SymbiFlow before updating the golden Verilog results and it did pass.

For testing purposes I've made the fasm2bels submodule in https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1729 point to this PR. (Previously the CI failed due to RapidWright and Java issues, I've rebased and re-ran it again)

BUFHCE route-through are indeed handled in the cleanup stage. Once a route-through BUFHCE is identified it is removed (BEL) and its input and output nets are joined and re-routed. This is necessary to keep integrity of all fasm2bels data structures. The resulting net preserves its route as it is derived from the list of active PIPs which doesn't change. The output Verilog netlist and XDC do not contain any mentions of any route-through BUFHCE. Neither does the interchange output.