Negative Edge Sensitive Events Being Uploaded as Positive Edge Sensitive Events

[WGeckle80]

Hello, I'm having an issue with negative edge sensitive events in f4pga. I can't remember which version I installed, but I installed f4pga back in early October 2023, yosys --version yields a version Yosys 0.27+22, and openFPGALoader --Version yields openFPGALoader v0.8.0. If there's any other software significant to this report I will respond accordingly.

I first encountered this when completing a sequential multiplier, where the controller should be sensitive to the positive edge of the clock, and the data path should be sensitive to the negative edge. Correct behavior is simulated using a testbench with Icarus Verilog, but functionality broke when bringing it to the Basys3, and it only broke more the more I tried to fix it. Turns out it's because both the controller and data path were acting on the positive edge of the clock.

For this simple example demonstrating the issue, I start with the module

module edge_test(output reg state,
                 output clk_ind,
                 input clk);
    always @(negedge clk) begin
        state <= !state;
    end

    assign clk_ind = clk;
endmodule

I write the constraints file (external 1 Hz clock is used because I don't feel like making a clock divider for this example).

# Map clk to a JA1.
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports clk]

# Map the clock indicator to the leftmost LED.
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports clk_ind]

# Map the current state indicator to the second leftmost LED.
set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports state]

I write the makefile according to the docs (using basys3).

current_dir := ${CURDIR}
TARGET := basys3
TOP := edge_test
SOURCES := ${current_dir}/edge_test.v

XDC := ${current_dir}/constraints.xdc

include ${HOME}/fpga/f4pga-examples/common/common.mk

I run make and upload the bit file using openFPGALoader -b basys3 build/basys3/edge_test.bit.

When running the design, the state LED changes on the positive edge rather than the negative edge as specified. Sorry about no video, I'm not sure how to reasonably upload a video to a Github issue.

Edit: I can't even fix this by trying to force negative edge sensitivity through positive edge sensitivity of an inverted clock on-board. The only way I have found to make negative edge sensitivity work is to invert the clock signal using an external inverter, then have the output of the inverter as an input through a PMOD pin alongside the non-inverted clock.