chipsalliance / firrtl-spec

The specification for the FIRRTL language
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[patch] Define Circuit Subcomponents #150

Closed mmaloney-sf closed 11 months ago

mmaloney-sf commented 11 months ago

Adds a section defining Circuit Subcomponents.

This notion is latent in the implementations, but is central to FIRRTL's semantics.

Intuitively, subcomponents are what you "dot into" or "index into". Eg, c[0].x is a reference to a subcomponent of a circuit component c.

Circuit subcomponents unify the notion of references, both static (sub-index and sub-field) and dynamic (sub-access). They are the entities which are the targets of a connect (... I believe this is a categorical statement). They are also important for reasoning about the initialization coverage of a module definition.

mmaloney-sf commented 11 months ago

For clarity, the direct subcomponent relation needs to be defined on the cross product of the kind and type of components.

There are only seven kinds. Since there are infinitely many types, we need to break them into a finite number of cases:

The first case is the grab bag of types which don't give rise to proper subcomponents.

The second case, vectors, splits up in the "obvious" way: you get one direct subcomponent per element in the vector and each has the base type.

The third case, bundles, is trickier because of flips. It still splits up in the "obvious" way: each field gives rise to a direct subcomponent with the field type of the corresponding field. However, the flip can change the subcomponent's kind.

When indexing into wires, nodes, and registers the kind never changes. When indexing into instances and memories, the subcomponents are as if you are "viewing" the port from the outside. The effect on kinds is a bit confusing at first glance, but it should check out when you work through the logic. (Or else be exactly backwards. As a matter of policy, I refuse to make guarantees I get my orientations correct. Ever.) Remember: output ports need to be driven and input ports drive. You need to ignore the fact that output and input suggest an absolute orientation. It's really hard to put into words -- work through this section carefully to see what I mean.

mmaloney-sf commented 11 months ago

I took what I had written up and cleaned it up a bit (apologies to @seldridge and @dtzSiFive for having to read my initial draft!):

mmaloney-sf commented 11 months ago

I also identified a few quirks: