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chipsalliance / firrtl-spec

The specification for the FIRRTL language
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[major] No abstract reset on extmodule. #181

Closed dtzSiFive closed 3 weeks ago

dtzSiFive commented 6 months ago

Align extmodule port requirements re:abstract reset to match those on "public".

seldridge commented 6 months ago

This one has users and, after talking with @dtzSiFive, it would be better to hold off on this for 4.0.0 so we can figure out how to get Chisel to stop emitting this.

darthscsi commented 2 months ago

so we can figure out how to get Chisel to stop emitting this.

Is it Chisel or code bases using it which do this? If it's just code-bases and there is nothing in Chisel forcing this, then that's an easier transition.

jackkoenig commented 2 months ago

Is it Chisel or code bases using it which do this? If it's just code-bases and there is nothing in Chisel forcing this, then that's an easier transition.

Chisel does not do this, the only things that get abstract reset automatically in Chisel are normal Modules (i.e. not extmodules) that are not the top module.