Open dtzSiFive opened 1 year ago
One candidate detail to include in such a rationale would be the motivation around some of the reference type design (under assumption it's merged of course), probably in general but specifically regarding input probe types. Request: https://github.com/chipsalliance/firrtl-spec/pull/75#discussion_r1127099637
We should add a place to document the "Rationale" for FIRRTL's design, perhaps in the spirit of MLIR's rationales: https://mlir.llvm.org/docs/Rationale/ .
This has been proposed and requested by a number of folks actively contributing to the specification, and let's start sorting out what this might look like and where.