Incorrect "reference not declared" message - Githubissues

chipsalliance / firrtl

Flexible Intermediate Representation for RTL

https://www.chisel-lang.org/firrtl/

Apache License 2.0

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Incorrect "reference not declared" message #1914

Open aswaterman opened 4 years ago

aswaterman commented 4 years ago

Checklist

[x] Did you specify the current behavior?
[x] Did you specify the expected behavior?
[x] Did you provide a code example showing the problem?
[x] Did you describe your environment?
[x] Did you specify relevant external information?

What is the current behavior?

Compilation of the following .fir file fails with error @[Mem.scala 41:20]: [module SyncReadMemWriteCollisionTester] Reference m1 is not declared.

SyncReadMemWriteCollisionTester.fir.txt

What is the expected behavior?

Successful compilation.

Steps to Reproduce

Pass attached .fir file to Firrtl compiler.

Your environment

Firrtl commit c07da8a581789b88f7e6ffc98c8e810565034ad9 (yes, kind of old)

aswaterman commented 4 years ago

PS. The bug doesn't manifest if you interpose a dummy node between _T_4 and the second mem's ports, i.e., replace the last two lines with

node tmp = _T_4
read mport rd1 = m1[tmp], clock @[Mem.scala 46:20]
write mport _T_6 = m1[tmp], clock