Open aswaterman opened 4 years ago
PS. The bug doesn't manifest if you interpose a dummy node between _T_4
and the second mem's ports, i.e., replace the last two lines with
node tmp = _T_4
read mport rd1 = m1[tmp], clock @[Mem.scala 46:20]
write mport _T_6 = m1[tmp], clock
Checklist
What is the current behavior?
Compilation of the following .fir file fails with error
@[Mem.scala 41:20]: [module SyncReadMemWriteCollisionTester] Reference m1 is not declared.
SyncReadMemWriteCollisionTester.fir.txt
What is the expected behavior?
Successful compilation.
Steps to Reproduce
Pass attached .fir file to Firrtl compiler.
Your environment
Firrtl commit c07da8a581789b88f7e6ffc98c8e810565034ad9 (yes, kind of old)