VerilatorEmitter

[sequencer]

I think should have a general Verilator Emitter to unify "chisel-tester", "chisel-tester2", "chiselTests", "firrtlTests", "rocket-chip emulator", "hardfloat FMA tests", and other possible emulators to provide users a good interface for simulation generation.

So I'm proposing creating a VerilatorEmitter for this job. @ekiwi also proposed this idea from https://github.com/chipsalliance/chisel3/pull/1925#issuecomment-848437126, and I also wanna implement this, since I have implemented Scala-based Verilator tests at least 4 times... I really think we need unify this API!!!

Another good thing is, in this Emitter, we can also emit a configuration file for coverage/formal annotations, and give Verilator ability to expose internal signals via annotation.

After finishing this, chisel-tester and chisel-tester2 can use this as an backend, while they only serve as a frontend. And users can create their fast-speed simulation tools to speed up their design specific simulation jobs(like rocket-chip and hardfloat).

It should cover most of verilator usages to simplify user flow in hardward simulation.

By the way I think, in the simulation area, SpinalHDL Sim did a better job than us. Maybe we need absorb some ideas(at least JNA interface) from it.

So I'm proposing adding VerilatorEmitter in FIRRTL, and also propose other non-free simulators as standalone plugin.

Checklist

• [x] Did you write out a description of the feature you want to see?
• [x] Did you look around for any related features?
• [ ] Did you specify relevant external information?

Feature Description

New feature: VerilatorEmitter

Type of Feature

• new feature/API

Related Features

None

External Information

None

[ekiwi]

@sequencer could you share some of your use cases with us? Is this only for interfacing with Verilator from Scala or also from C++?

I am playing around with a new simulator interface for chisel test on this branch: https://github.com/ekiwi/chisel-testers2/blob/firrtl-sim-interface/src/main/scala/chiseltest/simulator/Simulator.scala

[sequencer]

could you share some of your use cases with us?

Sorry, currently I have no enough time working on the use cases. I will work on this next month.

Is this only for interfacing with Verilator from Scala or also from C++?

I think C++ should also be included, if not, the only way seems to be only compiling Verilog to a library and let downstream handling linking script?

I am playing around with a new simulator interface for chisel test on this branch: https://github.com/ekiwi/chisel-testers2/blob/firrtl-sim-interface/src/main/scala/chiseltest/simulator/Simulator.scala

Great! I have some idea about this. I will share it on this thread when I have time.