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chipsalliance / firrtl

Flexible Intermediate Representation for RTL
https://www.chisel-lang.org/firrtl/
Apache License 2.0
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Rewrite Verilog Emitter #578

Open azidar opened 7 years ago

seldridge commented 5 years ago

While possibly putting too much into a PR to fix this, I'd argue that any Verilog Emitter rewrite would be a good candidate for subclassing Stage. That can happen as a PR before this or as part of this PR.