Basically, emit them in Verilog like you'd emit UInt<n> -- don't flatten them, not even on ports.
It's not inconceivable that we could specialize Vec[Bool] in Chisel instead, but someone's got to do this to provide decent simulation performance. This is probably the single most profitable simulation performance optimization beyond DCE.
azidar
commented
4 years ago
Basically, emit them in Verilog like you'd emit UInt<n> -- don't flatten them, not even on ports.
It's not inconceivable that we could specialize Vec[Bool] in Chisel instead, but someone's got to do this to provide decent simulation performance. This is probably the single most profitable simulation performance optimization beyond DCE.