The Lattice Nexus devices don't have inversion parameters; instead they use INV cells for inversion (ECP5 would also do this if we copied the vendor tools implementation). I think older ISE-rather-than-Vivado Xilinx parts might have done this sometimes too?
If we want to support this pattern; then the schema might want to define an inverter cell type (and input/output port names); similar to how it defines constant driver cell types.
The Lattice Nexus devices don't have inversion parameters; instead they use
INVcells for inversion (ECP5 would also do this if we copied the vendor tools implementation). I think older ISE-rather-than-Vivado Xilinx parts might have done this sometimes too?example: https://github.com/YosysHQ/yosys/blob/master/techlibs/nexus/brams_map.v#L56-L65
If we want to support this pattern; then the schema might want to define an inverter cell type (and input/output port names); similar to how it defines constant driver cell types.