Initial BEL and site design discussion.

chipsalliance / fpga-interchange-schema

https://fpga-interchange-schema.readthedocs.io/

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Initial BEL and site design discussion. #26

Closed litghost closed 3 years ago

litghost commented 3 years ago

@vaughnbetz FYI, discussion of BEL boundary modelling of Stratix II and 10.

To view images inline, view here: https://github.com/litghost/fpga-interchange-schema/blob/add_bel_and_site_design/docs/bel_and_site_design.md

mithro commented 3 years ago

Just FYI - the paper at https://www.eecg.utoronto.ca/~kmurray/titan/fpl_13_titan.pdf has some information about modeling the Stratix IV ALM. Screenshot from 2021-04-08 08-22-37

litghost commented 3 years ago

Just FYI - the paper at https://www.eecg.utoronto.ca/~kmurray/titan/fpl_13_titan.pdf has some information about modeling the Stratix IV ALM.

So the BEL design you've shown lumps the carry and the LUT elements, which is not a good choice IMO for an interchange representation. Too wide of a BEL boundary.