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chipsalliance / fpga-interchange-schema

https://fpga-interchange-schema.readthedocs.io/
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Need simple MUX2 descriptions in device resources #29

Open litghost opened 3 years ago

litghost commented 3 years ago

Many fabrics have simple 2-input 1-select line muxes located in the SLICE site. These appear in 7-series (MUXF7, MUXF8), US+ (MUXF7, MUXF8, MUXF9) and in QuickLogic EOS S3 (mux controlled by QDS and FS). While there should be cell elements to be explicitly placed at those BEL locations, there are some cases where having meta-data on these simple selector muxes are important. For 7-series and US+, this is needed to handle unbalanced MUX tree cases (see https://github.com/daveshah1/nextpnr-xilinx/blob/d40ffba7b34d0bd6ae7d62d1bf849f8ec4d1da78/xilinx/pack.cc#L257-L294) and in QuickLogic EOS S3 to configure the QDS line to choose either the output of the LUT3/MUX8x3 BEL or the QDI line implicitly.

This work is not critical for 7-series or US+, but is likely fairly important for QuickLogic EOS S3 support.

mkurc-ant commented 3 years ago

One idea of solving the issue is extending the concept of route-through BELs. Such a BEL should have its pins marked as eg. "route input", "route output" and "others". The "others" wouldn't be subjected to route-through at all but instead they would have annotations saying "if the input pin A is to be routed to the output pin B then route me to VCC/GND".