While looking into the clock routing problem, I remeberred that UltraScale+ clock routing has some special requirements (for many simpler devices a minimal-PIP BFS avoiding general routing gives good enough results).
In particular:
clocks must first be routed from the BUFG to a chosen clock root, picked to be in the centre of the design, using "routing" type resources
"distribution" type resources must then be used to fan the clock out to columns, where it is then routed using the dedicated column globals to sites
The big question is how, and whether, we should encode this relatively complex logic into the interchange format. A set of rules for globals that says "first use this wire type to a point; and then that wire type" seems like something that might be useful, although I'm not sure if this is going to reliably pick a suitable clock root.
While looking into the clock routing problem, I remeberred that UltraScale+ clock routing has some special requirements (for many simpler devices a minimal-PIP BFS avoiding general routing gives good enough results).
In particular:
The big question is how, and whether, we should encode this relatively complex logic into the interchange format. A set of rules for globals that says "first use this wire type to a point; and then that wire type" seems like something that might be useful, although I'm not sure if this is going to reliably pick a suitable clock root.
reference: https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf