Closed acomodi closed 3 years ago
@gatecat once we land the test architecture PR we could start adding timing information, i.e. land this PR. What is there on the nextpnr's plate that is missing in order to use the timing information?
The biggest issue is going to be developing a fast RC timing model. I would suggest prototyping this in Python using the python-fpga-interchange libraries before we go straight into the nextpnr side.
LGTM, merging
This PR is an initial attempt at adding specifications for timing delays to the schema.
It still requires further discussion around the details and also some practical testing before being approved and checked in.