Allow macro expansions conditional on parameter match

[gatecat]

To give a concrete example of why this is needed, consider the following design for xczu2eg-sbva484-2-e in Vivado:

module top(
    input I,
    output O_SSTL, OB_SSTL,
    output O_LVDS, OB_LVDS
);
    OBUFDS buf_sstl (.I(I), .O(O_SSTL), .OB(OB_SSTL));
    OBUFDS buf_lvds (.I(I), .O(O_LVDS), .OB(OB_LVDS));
endmodule

set_property IOSTANDARD LVCMOS18 [get_ports I]
set_property IOSTANDARD DIFF_SSTL18_I [get_ports O_SSTL]
set_property IOSTANDARD LVDS [get_ports O_LVDS]

set_property PACKAGE_PIN G5 [get_ports I]
set_property PACKAGE_PIN B2 [get_ports O_SSTL]
set_property PACKAGE_PIN T3 [get_ports O_LVDS]

Even though both the SSTL and LVDS output buffers are instantiated as OBUFDS, the SSTL buffer expands to OBUFDS_DUAL_BUF being pseudo-differential whereas the LVDS one remains as OBUFDS:

This adds support for this kind of conditionality to the interchange schema.