In the Intel ALM structure, there is what is essentially a routing bel (named MODE) with multiple outputs that controls the connectivity of different LUT and mux inputs in order to implement various modes:
It can't be split into several single output muxes because there are only a total of 16 possible permutations (even though Quartus does show it as 4 3-input muxes, not all permutations are legal).
Examples of some of the permutations that are possible (mistral doesn't document all of them yet):
I think the easiest way to implement this will be to allow routing bels to have multiple outputs, and add an extra field containing valid combinations of PIPs for these bels.
This is not a priority until we want to do Intel support via the interchange format, but it's worth bearing in mind.
In the Intel ALM structure, there is what is essentially a routing bel (named
MODE) with multiple outputs that controls the connectivity of different LUT and mux inputs in order to implement various modes:https://github.com/Ravenslofty/mistral/blob/master/docs-html/_images/lab-cell.svg
It can't be split into several single output muxes because there are only a total of 16 possible permutations (even though Quartus does show it as 4 3-input muxes, not all permutations are legal).
Examples of some of the permutations that are possible (mistral doesn't document all of them yet):
https://github.com/Ravenslofty/mistral/blob/master/docs-html/_images/lab-modes.svg
I think the easiest way to implement this will be to allow routing bels to have multiple outputs, and add an extra field containing valid combinations of PIPs for these bels.
This is not a priority until we want to do Intel support via the interchange format, but it's worth bearing in mind.