Following some IRC discussions with @mithro about different wire/node mapping representations, it was suggested that we could split that out of the main schema to make it easier to add new representations, like the future graph folding work from BYU.
At the moment, the wires/nodes are a totally separate schema but I'd be interested in knowing if there was a way of integrating it better.
Two examples are currently included, the original flat structure and my partially deduplicated structure from the tests in Xilinx/RapidWright#176 (towards the end of the discussion).
Following some IRC discussions with @mithro about different wire/node mapping representations, it was suggested that we could split that out of the main schema to make it easier to add new representations, like the future graph folding work from BYU.
At the moment, the wires/nodes are a totally separate schema but I'd be interested in knowing if there was a way of integrating it better.
Two examples are currently included, the original flat structure and my partially deduplicated structure from the tests in Xilinx/RapidWright#176 (towards the end of the discussion).