Choice of bel pins for a cell pin

[gatecat]

Consider a Xilinx CARRY8. The DI[i] cell pins (i≠4) can map either to an 'aX' bel pin or a DIi bel pin:

(set_property LOCK_PINS {DI[1]:DI1} [get_cells carry_i])

(set_property LOCK_PINS {DI[1]:BX} [get_cells carry_i])

Currently, although multiple bel pins can map to a single cell pin, there is no way to specify that the site router is free to choose any of them (except for LUTs which are implicitly assumed to be permutable based on the LUT bel info). If one cell pin maps to multiple bel pins at the moment, all of them will be routed (as is needed for BRAM, for example).

I see three ways of solving this:

• not supporting it, and adding virtual site pips to implement the choice of routing, with conversion necessary when generating a DCP or otherwise interfacing with the Xilinx ecosystem
• adding it as an explicit special case in its own right
• treating it as a special case of the parameter bel pin mapping rules (basically saying that the site router is free to change this parameter and hence the mapping as it likes).

[gatecat]

A similar situation exists with the CASC bel pin of Versal LUTs that can be used as a LUT input in some cases, which might create some interesting interactions with the current implicitly permutable LUTs...

set_property LOCK_PINS {I0:CASC} [get_cells lut_i]