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chipsalliance / fpga-interchange-schema

https://fpga-interchange-schema.readthedocs.io/
Apache License 2.0
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Add Bel pins clocking information #66

Open acomodi opened 2 years ago

acomodi commented 2 years ago

With the ongoing effort on adding the FPGA interchange support to VPR, some additional data would be required in the device resources (VTR docs) around the BEL pins, specifically about whether they are clock-related.

Possibly there would be an additional enum or a union added here to specify whether the bel pin is clock-related.

It might be possible to indirectly get this information from the wire type, following the routing connection from/to the BEL pin and, if a wire appears to be corresponding to the global clock network, than the connected BEL pins would be labeled as clock pins. In general, having an explicit attribute would simplify handling this information

clavin-xlnx commented 2 years ago

RapidWright has added a BELPin.isClock() method in the 2021.2.0 release.