Open kboronski-ant opened 2 years ago
Looks like there's an issue that's related to this PR: https://github.com/chipsalliance/fpga-interchange-schema/issues/44
@clavin-xlnx I moved the BEL locations to DeviceResources. I made an extra structure called PrimLibsExtra
that should hold any data that relates to primitive libraries that can't be expressed within LogicalNetlist
.
Structures relevant for macro expansions are insufficient to specify precise locations for cell instances. This is an issue with expansions like DRAM, which can contain multiple cells of the same type (eg. MUXF7), yet these cells have to be wired together in a specific way to avoid ending up with unroutable placements.
This PR proposes a solution to that issue with
CellInstance
struct now providing a list of acceptable bindings.