There is a deficiency in the schema for placed (but not routed) designs, specifically for AMD/Xilinx-targeted devices. After placement, Vivado will leave individual route nodes as clock tree decision points to enable the router to route the clock tree spine. Currently, there is no way to represent these individual nodes. This PR adds that capability as outlined in Xilinx/RapidWright#134 and more recently encountered in Xilinx/RapidWright#464.
There is a deficiency in the schema for placed (but not routed) designs, specifically for AMD/Xilinx-targeted devices. After placement, Vivado will leave individual route nodes as clock tree decision points to enable the router to route the clock tree spine. Currently, there is no way to represent these individual nodes. This PR adds that capability as outlined in Xilinx/RapidWright#134 and more recently encountered in Xilinx/RapidWright#464.