There are appears to be a systematic issue in nextpnr-fpga-interchange where LUT INIT strings don't always match up with the number of pins expected. Below is an example warning from Vivado, however, attached is a design that contains several instances where these warnings are present in the output after converted to a DCP.
CRITICAL WARNING: [Designutils 20-756] Invalid physical equation for the F6LUT bel in site SLICE_X60Y226. The original INIT is '6996966996696996'. The logical cell is 'LUT6_28e'. Reason: The bit width of the INIT value does not match the number of used input pins '4'. Please verify that all required logical pins are used for this cell.
Bel 22: element name: 'F6LUT'
Attr: 'EQN' Value: 64'h6996966996696996
Pin : index 0: A1 : Logical net: 'nb4e'
Pin : index 1: A2 : Logical net: 'nb82'
Pin : index 2: A3 : Logical net: 'nba4'
Pin : index 3: A4 : Logical net: 'nb4a'
Pin : index 5: A6 : VCC Physical-only net
Pin : index 6: O6 : Logical net: 'nbc5'
Inst: 'LUT6_28e'
CellType: 'LUT6'
Pin Swappable:
Inst term 'I5' ('I5') -> Bel pin 'A1' (by placer)
Inst term 'I4' ('I4') -> Bel pin 'A2' (by placer)
Inst term 'I1' ('I1') -> Bel pin 'A3' (by placer)
Inst term 'I0' ('I0') -> Bel pin 'A4' (by placer)
Not assigned -> Bel pin 'A5'
Not assigned -> Bel pin 'A6'
example.zip
There are appears to be a systematic issue in nextpnr-fpga-interchange where LUT INIT strings don't always match up with the number of pins expected. Below is an example warning from Vivado, however, attached is a design that contains several instances where these warnings are present in the output after converted to a DCP.