Add US+ BRAM test - Githubissues

chipsalliance / fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format

https://chipsalliance.github.io/fpga-interchange-tests

ISC License

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Add US+ BRAM test #99

Closed kboronski-ant closed 2 years ago

kboronski-ant commented 2 years ago

This PR adds the following FAILING tests for Ultrascale+ family (ZCU104):

BRAM (with differential clock):

ram_36bit

nextpnr complains about not enough LUT cells being available. Depite that it does seem to infer the usage of BRAM as it's reported that one BRAM cell was used.

acomodi commented 2 years ago

This is fixed with https://github.com/YosysHQ/nextpnr/pull/932. Once it gets merged, and a conda package is generated, we can proceed by merging this PR