Xilinx's pre-synthesized tests for Ultrascale+

[kboronski-ant]

Context: We want to measure performance of nexpnr-fpga_interchange for some of the designs generated by Xilinx: https://github.com/chipsalliance/fpga-interchange-tests/issues/128

• Adds basic support for xczu7ev device along with "xczu7ev" board for testing purposes.
• Bumps nextpnr-fpga_interchange version to latest main available in conda
• Adds nextpnr-fpga-interchange-presynth toolchain for handling pre-synthesized designs.
• Changes edalize version to a fork that supports nextpnr-fpga_interchange in the nextpnr edatool.
• Adds three pre-synthesized designs for an xczu7ev device:
  • gnl_2_4_3_1.3_gnl_2000_03_3_80_80
  • gnl_2_4_5_1.3_gnl_2500_03_5_80_80
  • gnl_2_4_5_2.0_gnl_2000_08_5_80_80

[kboronski-ant]

The tests I've added fail due to outdated nextpnr conda package. The latest release of nextpnr should work. Some tests are generated, even tho they shouldn't be. Looks like skip_toolchains field gets ignored when running exhaustive tests for everything. Other failures seem to be unrelated to the contents of the PR judging so far by the logs. Last CI run on main was 16 days ago - did something broke since then?

[mithro]

FYI - I think we all agreed that we need a better name than "pre-synthesized" maybe "already-synthesised"?