chipsalliance / fpga-tool-perf

FPGA tool performance profiling
https://chipsalliance.github.io/fpga-tool-perf
Apache License 2.0
101 stars 30 forks source link

Add support for RapidWright #516

Open tmichalak opened 1 year ago

tmichalak commented 1 year ago

The target is to be able to measure the performance of various routing algorithms done with the help of RapidWright. However, first we need to integrate RW with the fpga-tool-perf.

tmichalak commented 1 year ago

@clavin-xlnx could you please update the description and add more details and describe which algorithms you would like to add?

clavin-xlnx commented 1 year ago

RapidWright has a router called RWRoute. It only supports UltraScale+ devices and can be run in both timing-driven and non-timing-driven modes and depends on the design being fully placed (and intra-site nets are routed). From what I remember, nextpnr-interchange does not yet have the ability to output a placed (but not routed) design yet. So, to run RWRoute, the design would need to be unrouted first. For example, if a from nextpnr-interchange was placed and routed and saved as an Interchange fileset, RWRoute could be run with the following RapidWright code:

        EDIFNetlist netlist = LogNetlistReader.readLogNetlist(logNetlistFileName);
        Design design = PhysNetlistReader.readPhysNetlist(physNetlistFileName, netlist);

        // TODO - Remove once nextpnr can export placed-only design
        design.unrouteDesign();

        RWRoute.routeDesignFullNonTimingDriven(design);
        // Timing-driven option: RWRoute.routeDesignFullTimingDriven(design);