Add parameters to library cells

chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format

ISC License

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Add parameters to library cells #133

Closed mtdudek closed 2 years ago

mtdudek commented 2 years ago

This PR adds parameters to primitive cells. This data can be useful in PR tools, to mark which ports are clocks, which clock interacts with cell port, how nets are internally connected. Signed-off-by: Maciej Dudek mdudek@antmicro.com