Testarch generator: add LUT param definition and use single PAD

chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format

ISC License

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Closed acomodi closed 3 years ago

acomodi commented 3 years ago

This PR adds the following:

parameter definition for the LUT cell
merge IPAD and OPAD in a single PAD (similarly to how it is usually seen in series7 and other arches). This is to better understand and implement the IO handler in the VTR interchange development.