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chipsalliance / python-fpga-interchange

Python interface to FPGA interchange format
ISC License
41 stars 12 forks source link

Improve IO pads complexity handling #144

Closed acomodi closed 2 years ago

acomodi commented 2 years ago

This PR adds complexity to the IO sites, allowing for more complex cases, more similar to real devices.

For instance, it generates three different IO types:

Additionally, this PR adds another SLICE for each CLB