amitgargmentor
commented
5 years ago resolved by passing --isa rv32i arguement.
Closed amitgargmentor closed 5 years ago
amitgargmentor
commented
5 years ago resolved by passing --isa rv32i arguement.
While runing the coverage test, i see that addiw instruction is illegal instruction. i think the reason for that is cfg.instruction_template doesnt have ADDIW instruction. Did anyone face this issue?
Command used: python cov.py --dir out_2019-10-31/spike_sim --v
Log:
UVM_INFO ./src/riscv_instr_gen_config.sv(430) @ 0: reporter [cfg] riscv_instr_pkg::supported_privileged_mode = 3
UVM_INFO ./test/riscv_instr_cov_test.sv(45) @ 0: uvm_test_top [uvm_test_top] 1 CSV trace files to be processed
UVM_INFO ./test/riscv_instr_cov_test.sv(49) @ 0: uvm_test_top [uvm_test_top] Processing CSV trace[0]: out_2019-10-31/spike_sim/riscv_arithmetic_basic_test.0.csv
** Warning: (vsim-3829) Non-existent associative array entry. Returning default value.
Time: 0 ns Iteration: 61 Process: /uvm_pkg::uvm_task_phase::execute/#FORK#143(#ublk#215181159#143)_7fefe8304e7 File: ./test/riscv_instr_cov_test.sv Line: 130
UVM_INFO ./test/riscv_instr_cov_test.sv(130) @ 0: uvm_test_top [DBG] Sample illegal opcode: 6 []
UVM_INFO ./test/riscv_instr_cov_test.sv(79) @ 0: uvm_test_top [uvm_test_top] Found illegal instr: addiw [addiw,zero,0,zero,0,,,fffff88f,"addiw zero, zero, -771",0000000080000004,cfd0001b,,
]
** Warning: (vsim-3829) Non-existent associative array entry. Returning default value.
Time: 0 ns Iteration: 61 Process: /uvm_pkg::uvm_task_phase::execute/#FORK#143(#ublk#215181159#143)_7fefe8304e7 File: ./test/riscv_instr_cov_test.sv Line: 130
UVM_INFO ./test/riscv_instr_cov_test.sv(130) @ 0: uvm_test_top [DBG] Sample illegal opcode: 6 []
UVM_INFO ./test/riscv_instr_cov_test.sv(79) @ 0: uvm_test_top [uvm_test_top] Found illegal instr: addiw [addiw,ra,0000000000000001,zero,0,,,1,"addiw ra, zero, 1",0000000080000010,0010009b,,
]
CSV file: instr,rd,rd_val,rs1,rs1_val,rs2,rs2_val,imm,str,addr,binary,csr,mode jal,zero,0,t0,,,,,jr t0,0000000000001010,00028067,, lui,zero,0,,,,,18,"lui zero, 0x18",0000000080000000,00018037,, addiw,zero,0,zero,0,,,fffff88f,"addiw zero, zero, -771",0000000080000004,cfd0001b,, slli,zero,0,zero,0,,,15,"slli zero, zero, 15",0000000080000008,00f01013,, li,,,,,,,,"li zero, 15",000000008000000c,00f00013,, addiw,ra,0000000000000001,zero,0,,,1,"addiw ra, zero, 1",0000000080000010,0010009b,, slli,ra,0000000080000000,ra,0000000080000000,,,31,"slli ra, ra, 31",0000000080000014,01f09093,, lui,sp,00000000000f6000,,,,,f6,"lui sp, 0xf6",0000000080000018,000f6137,, addiw,sp,00000000000f6015,sp,00000000000f6015,,,21,"addiw sp, sp, 21",000000008000001c,0151011b,,