chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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It has warning for running coverage #406

Closed danghai closed 4 years ago

danghai commented 4 years ago

It has warning for running coverage. Step to reproduce:

python3 run.py --test riscv_arithmetic_basic_test --iss spike --simulator qrun -o qruncov -v
python3 cov.py --dir qruncov/spike_sim --simulator qrun -v

Log file:

 UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] pc=ffffffff8000e0dc
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] instr=beq
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] gpr=
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] csr=
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] binary=36fb8763
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] mode=
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] instr_str=beq     s7, a5, 878
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] operand=s7,a5,878
# ** Warning: (vsim-3829) Non-existent associative array entry. Returning default value.
#    Time: 0 ns  Iteration: 61  Process: /uvm_pkg::uvm_task_phase::execute/#FORK#143(#ublk#215181159#143)_7feff02ee09 File: /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv Line: 172
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(80) @ 0: uvm_test_top [] ----------------------------------------------------------
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] pc=ffffffff8000e0e0
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] instr=c.li
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] gpr=a5:00000002
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] csr=
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] binary=00004789
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] mode=3
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] instr_str=c.li    a5, 2
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(84) @ 0: uvm_test_top [] operand=a5,2
# ** Warning: (vsim-3829) Non-existent associative array entry. Returning default value.
#    Time: 0 ns  Iteration: 61  Process: /uvm_pkg::uvm_task_phase::execute/#FORK#143(#ublk#215181159#143)_7feff02ee09 File: /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv Line: 172
# UVM_INFO /home/danghai/hhoangda/riscv-dv/test/riscv_instr_cov_test.sv(80) @ 0: uvm_test_top [] ------------------------------------
taoliug commented 4 years ago

please verify if it's fixed.

danghai commented 4 years ago

It works now