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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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README.md corrections for the new flow #54

Closed vandanaprabhu closed 5 years ago

vandanaprabhu commented 5 years ago

With reference to changes in New YAML based regression flow #46, these are my observations:

  1. README.md still uses -tool irun instead of ius for the new flow

  2. Also suggest adding "run.py --help" as a first step to show the user all the new options and what the arguments may be since the README.md doesn't quite cover the newer options

3.--help says you expect SO and CO as arguments for -so and -co but that doesn't work for me so I ended up passing an int after looking at the code. Not passing an argument doesn't work either so the intent of the arguments to these options is not clear in the --help or README.md

  1. --verbose VERBOSE doesn't work either so had to pass an int to get it going similar to 3 above

  2. Does it expect RISCV_GCC to be set? Any other variables besides SPIKE_PATH? This should be mentioned in the README too

scottj97 commented 5 years ago

For boolean options like these, python's argparse offers action='store_true' (instead of type=int).

taoliug commented 5 years ago

Thanks for reporting, I will take a look and get back to you.

danghai commented 5 years ago

I got the same issue relating to RISCV_GCC:

danghai@ubuntu:~/google/riscv-dv$ python3 run.py --test=riscv_page_table_exception_test --iss=spike
Processing regression test list : /home/danghai/google/riscv-dv/yaml/testlist.yaml, test: riscv_page_table_exception_test
Found matched tests: riscv_page_table_exception_test, iterations:2
Processing simulator setup file : /home/danghai/google/riscv-dv/yaml/simulator.yaml
Found matching simulator: vcs
Building RISC-V instruction generator
Running RISC-V instruction generator
Generating 2 riscv_page_table_exception_test
Please set the environment variable RISCV_GCC
taoliug commented 5 years ago

Just submitted PR #56 to address the issues, please let me know if there's anything else not working for you.

taoliug commented 5 years ago

I haven't tested with questa though, please let me know if you have issue running with questa.

danghai commented 5 years ago

Hi @taoliug , I create a PR to make it work for questa.

vandanaprabhu commented 5 years ago

The questa flow appears to be broken (hence the empty asm file) because of the spaces preceding the multiline vlog and opt options simulator.yaml file. When I changed these to tabs as shown below and the compile and sim worked Also the correct command is sv_seed (not svsejd )value is not being passed correctly it appears.

Let me know if you want me to create a pull request but I believe this should fix Hai’s issue.

Vandana

On Aug 1, 2019, at 3:55 PM, taoliug notifications@github.com wrote:

I haven't tested with questa though, please let me know if you have issue running with questa.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/google/riscv-dv/issues/54?email_source=notifications&email_token=AMWOBJESYTDZJCP6MODSAUTQCNSXXA5CNFSM4IIUKOMKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOD3MDOZQ#issuecomment-517486438, or mute the thread https://github.com/notifications/unsubscribe-auth/AMWOBJHPAFIV3P56GO64WJDQCNSXXANCNFSM4IIUKOMA.

taoliug commented 5 years ago

Please feel free to create a PR if it fixes the questa sim issue on your side. Thanks.