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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
1.02k stars 330 forks source link

Free RTL simulation tools for students #687

Closed NazerkeT closed 4 years ago

NazerkeT commented 4 years ago

Hi there, Recently, I have build support for a CVA6 core for 4 bitmanip subgroups and wanted to test them for validity. Coming to this point, I have found out that there is not actually any student licences that let full-stack RTL simulation. However, still want to believe to the good news and want to clarify :) Can I run this riscv-dv using some student licence from third-party RTL simulators? Or is there any other similar opportunity for System Verilog verification?

Best regards,

udinator commented 4 years ago

Hi @NazerkeT, if I understand you correctly, yes - to run the SystemVerilog riscv-dv generator you will need a license for any of the simulators that we support (VCS, IUS, Questa, DSim, Xcelium, or Riviera).

omerguzelelectronicguy commented 1 year ago

Is there any option at least just to create a torture assembly test without any simulation?

NazerkeT commented 1 year ago

@omerguzelelectronicguy So far nothing that I found or am aware of :(

But maybe in the last 2 years, there have been some advances in it, you might wanna search a bit more I guess 😅

Best wishes,