Closed berkkis closed 5 years ago
Do you want to disable compressed instruction in one test or all tests?
I tried to disable for all the tests. But if there is a test-specific solution I can use it as well.
Please try run riscv_non_compressed_instr_test test https://github.com/google/riscv-dv/blob/master/yaml/testlist.yaml#L83
If the processor doesn't support compressed instruction, you can disable it in the processor setting https://github.com/google/riscv-dv/blob/master/setting/riscv_core_setting.sv#L33
For the first link, I will try the riscv_non_compressed_instr_test. For the second link, that's what I've tried to do. But at the riscv_gcc compilation step, there were still compressed instructions from the instruction stream resulting in assembler error. My question is this an expected behavior.
./iss_sim -iss spike -isa rv64im -abi lp64
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S: Assembler messages: ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S:181: Error: unrecognized opcode `c.beqz s1,j__main_sub_1_1' ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S:25608: Error: unrecognized opcode `c.bnez a0,smode_accessible_umode_program_stack_p' Convert ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.bin /home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.o': No such file
This issue should be fixed by #81 , can you try again?
I am closing this issue for now, please let me know if it doesn't work for you.
Hi, Right now I am trying to generate tests with a subset of supported instruction group namely "rv64im". I would appreciate it if you could point out where I am wrong. 1)Following the README.md and manipulating riscv_core_settings.sv:
2)After, these commands are run
3)The problem is here. "iss_sim" outputs assembler errors regarding "C" extention. """
"""