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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
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Unimplemented CSR appears in the generated .S file #795

Open mykola-mmm opened 3 years ago

mykola-mmm commented 3 years ago

Hi everyone,

The version I'm working with: commit 5a79a54f8330c904eae98e51be55bbb55ac30c82 Here is my riscv_core_setting.sv:

// Implemented previlieged CSR list ifdef DSIM privileged_reg_t implemented_csr[] = { else const privileged_reg_t implemented_csr[] = { `endif // Machine mode mode CSR MSTATUS, // Machine status MISA, // ISA and extensions MTVEC, // Machine trap-handler base address // MSCRATCH, // Scratch register for machine trap handlers MEPC, // Machine exception program counter MCAUSE // Machine trap cause };

And here is base_testlist.yaml with my custom test:

  • test: test_arithmetics description: > Arithmetic instruction test, no load/store/branch instructions gen_opts: > +num_of_tests=100 +num_of_sub_program=5 +instr_cnt=2000 +no_csr_instr=0 +directed_instr_0=riscv_int_numeric_corner_stream,4 iterations: 1 gen_test: riscv_instr_base_test rtl_test: core_base_test

However, the generated code has csrr and csrw operaions with the 0x340 (MSCRATCH) register which I have disabled. Also, csrr and csrw operations with the 0x340 register present inside the body of most handlers:

instr_fault_handler: li x17, 0 csrw 0x340, x17 li x26, 0 0: csrr x17, 0x340

load_fault_handler: li x17, 0 csrw 0x340, x17 li x26, 0 0: csrr x17, 0x340

Is it a normal result? I am not sure that this is a bug but in my opinion, disabled CSRs should not appear inside the body of the program.

mykola-mmm commented 3 years ago

Upd: I have just realized that handlers I have mentioned are not used in my code so they are not the problem. However, csr operation with 0x340 appears inside the main func:

main: beq t5, t4, 5f lui a1, 335156 srai t2, a0, 18 remu a1, s9, a2 csrrwi t2, 0x340, 23