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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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Comparison with cycle-accurate Simulators #838

Open Username608 opened 2 years ago

Username608 commented 2 years ago

I'm having issues using the csv_compare method to verify that two traces are matching. I'm using Spike as a golden reference. However, Spike is instruction-accurate, while the RTL model is cycle-accurate. Because of this, the results of instructions are not necessarily written-back in program order (for example with a multi-cycle multiplier), which creates a discrepancy with respect to the Spike log. I could easily modify the comparison function to fix this, but I am asking to make sure I am not missing something, as this issue is something I suspect already came into consideration. Also, other verification projects make no changes to the csv_compare method. Am I missing something or is csv_compare dependent on in-order commit logs?

haibt15 commented 2 years ago

I have the same problem, the RTL model is cycle-accurate and my core have multi-cycles function unit (MCFU). So the result of RTL doesn't fit the Spike log, to solve that i only comparing only register value change. Should I do that to solve the problem?