chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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[Pygen] Fix typo in mseccfg_reg_t class #866

Closed aneels3 closed 2 years ago

aneels3 commented 2 years ago

Signed-off-by: aneels3 b150023ec@nitsikkim.ac.in

Fix #865