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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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limited randomization of the arguments for the instruction #884

Open ShraddhaDevaiya opened 2 years ago

ShraddhaDevaiya commented 2 years ago

Hello, I have generated few tests(riscv_arithmetic_basic_test, riscv_jump_stress_test and riscv_mmu_stress_test), and observed that there is lot of repetition in generated instructions(means there are very unique arguments with the same instruction). You can see here:

image

if you see addw instruction, it has same arguments or operands.

we can see different unique instruction , it is with the number of iterations. but in the single assembly file ,there are very few unique instruction in this respective.

can anyone please put some light on this or help in this?

aneels3 commented 2 years ago

Hi @ShraddhaDevaiya I think you might be using the shallow copied object for every randomization for that particular instructions class. If possible try copying the object as deepcopy and check the .S file