[pmp] riscv_pmp_test will set pmpcfg1 even if XLEN=64

[atsushi-shinbo-esoltrinity]

riscv_pmp_test will generate pmp_setup routine in the output code. When the target is rv64gc, this routine contains csrw pmpcfg1, rs1 instruction.

According to RISC-V specification, there is no pmpcfg1 register when XLEN=64. So, generated code is invalid.

riscv-privileged-20211203.pdf 3.7.1 Physical Memory Protection CSRs

For RV64, eight even-numbered CSRs, pmpcfg0, pmpcfg2, ..., pmpcfg14, hold the configurations for the 64 PMP entries, as shown in Figure 3.32. For RV64, the odd-numbered configuration registers, pmpcfg1, pmpcfg3, ..., pmpcfg15, are illegal.

How to reproduce

• Modify target/rv64gc/riscv_core_setting.sv as following,

  // Physical memory protection support
  -bit support_pmp = 0;
  +bit support_pmp = 1;

• Modify target/rv32imc/testlist.yaml as following,

• test: riscv_pmp_test gen_opts: >

• +pmp_num_regions=1

• +pmp_num_regions=16

• Run following command,

  python3 run.py --iterations 1 --seed 1 --target=rv64gc --isa=rv64gc --mabi=lp64 --test=riscv_pmp_test --simulator xlm --output out

• Refer to out/asm_test/riscv_pmp_test_0.S, and check there are following instructions,

  li x25, 0xf0f0f0f0f0f0f0f
  csrw 0x3a1, x25             (CSR 0x3a1 = pmpcfg1)

Versions

I am using following environment

• riscv-dv : 68e3bcac7293ac79067f0d8196bb973bd7c889cf
• Cadence Xcelium : 22.03