chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
997 stars 322 forks source link

VCS 2018 cannot generate , error Segmentation fault #915

Open huge12138 opened 1 year ago

huge12138 commented 1 year ago

An unexpected termination has occurred in /google-riscv-dv/out_2022-11-25/vcs_simv due to a signal: Segmentation fault

Command line: /google-riscv-dv/out_2022-11-25/vcs_simv +vcs+lic+wait +ntb_random_seed=935459861 +UVM_TESTNAME=riscv_instr_base_test +num_of_tests=2 +start_idx=0 +asm_file_name=out_2022-11-25/asm_test/riscv_arithmetic_basic_test -l out_2022-11-25/sim_riscv_arithmetic_basic_test_0.log +instr_cnt=10000 +num_of_sub_program=0 +directed_instr_0=riscv_int_numeric_corner_stream,4 +no_fence=1 +no_data_page=1 +no_branch_jump=1 +boot_mode=m +no_csr_instr=1