chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
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[cfg,gpr] reg constraint in riscv_gen_config. #922

Open SerLippo opened 1 year ago

SerLippo commented 1 year ago

Question: why is that cfg.ra, tp, sp, gpr, pmp_reg, scratch_reg can not be randomized to GP or RA??

Thanks

SerLippo commented 1 year ago

Is Assembler will treat those two regs differently? Here is the code:

constraint sp_tp_c { if (fix_sp) { sp == SP; } sp != tp; !(sp inside {GP, RA, ZERO}); !(tp inside {GP, RA, ZERO}); }

// This reg is used in various places throughout the generator, // so need more conservative constraints on it. constraint reserve_scratch_reg_c { !(scratch_reg inside {ZERO, sp, tp, ra, GP}); }

// These registers is only used inside PMP exception routine, // so we can be a bit looser with constraints. constraint reserve_pmp_reg_c { foreach (pmp_reg[i]) { !(pmp_reg[i] inside {ZERO, sp, tp, scratch_reg}); } unique {pmp_reg}; }

constraint gpr_c { foreach (gpr[i]) { !(gpr[i] inside {sp, tp, scratch_reg, pmp_reg, ZERO, RA, GP}); } unique {gpr}; }