PyFlow log trace to csv improvements and Renode ISS support

chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification

Apache License 2.0

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Closed mczyz-antmicro closed 1 year ago

mczyz-antmicro commented 1 year ago

This PR provides enhancements to the ISS used with PyFlow Instruction Generator:

Fixed logs created with spike in a scenario with multiple spaces and enabled parsing CSR writes from them
Log file names produced by run.py now follow the same convention
Added missing PC values to VeeR-ISS (a.k.a. whisper) log to CSV converter
Enabled Renode as an Instruction Set Simulator

tmichalak commented 1 year ago

@pradheepkaliraj could you take a look and let us know if there is something to be done here or if it is fine to be merged?