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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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no_load_store switching option #943

Open hyperion009 opened 1 year ago

hyperion009 commented 1 year ago

Hi It seems that the "no_load_stroe" option is not passed into member function gen_instr () like main_program[hart].gen_instr(.is_main_program(1), .no_branch(cfg.no_branch_jump)); seq.gen_instr(.is_main_program(0), .no_branch(cfg.no_branch_jump)); sub_program[i].gen_instr(.is_main_program(0), .no_branch(cfg.no_branch_jump)); which its' default is no_load_store =1 ,So, there is no load/store instruction in main program and subprogram, right? why?

thanks L.Y.F