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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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use ovpsim .Why is there no verbose log instruction #958

Open moyouth opened 1 year ago

moyouth commented 1 year ago

微信图片_20231007162940 微信图片_20231007162947 微信图片_20231007162951

eroom1966 commented 1 year ago

try running with the flags --help or --helpall there are a number of trace options, for example, I would recommend first selecting

--trace --tracechange

but there are many other trace options

moyouth commented 1 year ago

微信图片_20231010104511 ovpsim dont support --trace --tracechange，i add 2 commands in the picture,still no verbose log instruction

moyouth commented 1 year ago

try running with the flags --help or --helpall there are a number of trace options, for example, I would recommend first selecting

--trace --tracechange

but there are many other trace options 微信图片_20231010110822

duncangraham-Imperas commented 1 year ago

When you ask about verbose log instruction, what is it you are wanting to see?

There are two free products that include the OVP RISC-V reference models riscvOVPsim and riscvOVPsimPlus; both contain the same models but provide different features. You can obtain riscvOVPsimPlus from the OVP World website and you should be able to switch to using this in the riscv-dv infrastructure; this will provide instruction trace output; if that s what you are looking for?

moyouth commented 1 year ago

When you ask about verbose log instruction, what is it you are wanting to see?

There are two free products that include the OVP RISC-V reference models riscvOVPsim and riscvOVPsimPlus; both contain the same models but provide different features. You can obtain riscvOVPsimPlus from the OVP World website and you should be able to switch to using this in the riscv-dv infrastructure; this will provide instruction trace output; if that s what you are looking for? 微信图片_20231010170215

THANKS！！！！ using --iss=spike，the log in the picture like this： In the log, the first column is the PC value, the second column is the instruction, the third column is the identifier for general registers or control registers, and the fourth column is the value of the register.

i wanna see verbose log instruction when i use --iss=ovpsim. i dont use riscvOVPsimplus