ISS usage fixes - Githubissues

chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification

Apache License 2.0

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Closed mkurc-ant closed 11 months ago

mkurc-ant commented 11 months ago

This PR fixes usage of certain ISSes:

Parameterized Renode memory size
Detection of ECALL instruction in Renode and writing its occurrence to the execution log
Enabled unaligned load/store access in Renode and Spike
Added config for Whisper, configured memory map to allow unaligned load/store