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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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Fix Ctrl-C processing & use as lib with recent python versions #960

Closed cathales closed 10 months ago

cathales commented 11 months ago

Hello,

We are using riscv-dv with two patches to verify CVA6. We hope it will help everyone if those patches are made common.

  1. The simulation was still running after hitting Ctrl-C. With this PR it is correctly killed. It is a continuation of work from @yanicasa fixing the same issue for timeouts.
  2. We are using riscv-dv as a library with a relative path dv.scripts. Python 3.9 cannot find it albeit Python 3.7 had no issues finding it. To fix this, we found this link and added an empty __init__.py file.
JeanRochCoulon commented 10 months ago

Hello, Thank you to have reviewed and approved this PR. In OpenHW Group, and more precisely in CVA6 project, we are glad to use the riscv-dv project. We try to be synchronized with this repository by declaring it as submodule. As you know the drawback to declare it as submodule is that we are dependant of it. Today we would be pleased to ugrade the riscv-dv hash, but we are waiting for this PR merge since two weeks. It would be great if you cold merge it on master. It would unlock cva6 project.