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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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spike #961

Open riscv1111 opened 11 months ago

riscv1111 commented 11 months ago

Use spike to simulate random instruction flow, open the log and find that the result is stuck in an infinite loop.log display 4.exception trap_supervisor_ecall , epc 0x00000000000005ae；>>>>$xrv64i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0；6.0x0000000080013000 (0x0400006f) j pc+ 0x40