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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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The spike simulation gets stuck in an endless loop #962

Open riscv1111 opened 11 months ago

riscv1111 commented 11 months ago

b5059718bf132f513e09689f8bef2ad

kevinhe5 commented 11 months ago

I'm also experiencing the same issue. Could this be related to this issue: https://github.com/riscv-software-src/riscv-isa-sim/issues/555?

riscv1111 commented 10 months ago

I'm also experiencing the same issue. Could this be related to this issue: riscv-software-src/riscv-isa-sim#555?

How to solve this problem? https://github.com/chipsalliance/riscv-dv/commit/0c640e3a9eb37a9d28b7f21104d0024b7148d7cf