rv64gc failing spike due to exception trap_store_address_misaligned

[kevinhe5]

Hi, I'm running riscv-dv with run --test riscv_arithmetic_basic_test --simulator vcs --target rv64gc and its failing spike with this log after test_done is ran:

core   0: 0x0000000080009e8a (0x00004185) c.li    gp, 1
core   0: 3 0x0000000080009e8a (0x4185) x3  0x0000000000000001
core   0: 0x0000000080009e8c (0x00000073) ecall
core   0: exception trap_machine_ecall, epc 0x0000000080009e8c
core   0: >>>>  mtvec_handler
core   0: 0x000000008000b000 (0x0400006f) j       pc + 0x40
core   0: 3 0x000000008000b000 (0x0400006f)
core   0: >>>>  mmode_exception_handler
core   0: 0x000000008000b040 (0x000017f1) c.addi  a5, -4
core   0: 3 0x000000008000b040 (0x17f1) x15 0x000000008001fcf4
core   0: 0x000000008000b042 (0x0107b023) sd      a6, 0(a5)
core   0: exception trap_store_address_misaligned, epc 0x000000008000b042
core   0:           tval 0x000000008001fcf4
core   0: >>>>  mtvec_handler
core   0: 0x000000008000b000 (0x0400006f) j       pc + 0x40
core   0: 3 0x000000008000b000 (0x0400006f)
core   0: >>>>  mmode_exception_handler

corresponding to

mmode_exception_handler:
                  addi x15, x15, -4
                  sd  x16, (x15)
...

in the generated assembly. I see that x15 is supposed to be set to the address of the kernel_stack_end set at the beginning of the program

kernel_sp:        
                  la x15, kernel_stack_end

Is it supposed to be at that value when we get to mmode_exception_handler? It seems this address in x15 is overwritten during the program whenever a5 is used in the generated instructions, so when the mmode_exception_handler tries to save at whatever value is in x15/a5, the exception handler throws an unaligned address exception and just runs in a loop of exception handling until it eventually fails with

Access exception occurred while host was accessing memory on behalf of target (tohost = 0xffffffff80017c38):
Memory address 0xffff800178 is invalid

[zyx911126]

I meet the similar question, can you tell me the version of your riscv-dv and spike and do you slove this question now？

[dpetrisko]

May be related to this? https://github.com/chipsalliance/riscv-dv/pull/925