Open 5hayanB opened 10 months ago
I looked further into the problem and have found out that the riscv-dv
is generating the wrong .S
file. On compiling the the assembly file with
riscv64-unknown-elf-gcc -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles riscv_arithmetic_basic_test_0.S -I/dv/user_extension -T/dv/scripts/link.ld -o riscv_arithmetic_basic_test_0.o -march=rv32izicsr -mabi=ilp32
the compilation works and .o
object file is being created successfully. Why would riscv-dv
generate a the wrong assembly test when the --target rv32i
is already given? The riscv_arithmetic_basic_test
field of the testlist yaml even has +no_csr_instr=1
, meaning no CSR instruction is to be created and yet csr instructions are generated in the assembly file.
Seems like riscv-dv
broke with riscv64-unknown-elf-gcc
version 13.2.0
as I tested riscv-dv
with riscv64-unknown-elf-gcc
version 11.1.0
and is working. I am now changing issue topic to the specific problem at hand.
After loads of compiling and testing different tags of the riscv-gnu-toolchain, tags 2023.04.18
and up are incompatible with riscv-dv
as of yet. I do not know if I should leave the issue open to keep track of toolchain compatibility or close it to after finding out the working version. I will leave the issue open and let the maintainers take the required action as they see fit.
Hi @5hayanB, Could you figure out which version is working or why it was not working?
@Sai-Manish, I was able to find that the tags 2023.03.14
and below of the riscv-gnu-toolchain work with riscv-dv
. I think the problem is that riscv-dv
uses initial csr instructions in program initialization and assumes that the rv32i
extension supports csr extensions. However, the spec now states that the csr extensions be implemented in Zicsr
which is not a part of rv32i
which is also updated in the latest riscv-gnu-toolchain.
I am using the following command to generate arithmetic tests for
rv32i
targetHowever, I am receiving assembler errors at the compilation step
I verified the
.S
files generated bydv
and indeed that is the case. I tried emptyingimplemented_csr
inpygen/pygen_src/target/rv32i/riscv_core_setting.py
but to no avail. Do I need to specifyrv32iZicsr
to--target
?